1. Field of the Invention
The present invention relates to a method of managing semiconductor wafer processing and a process managing system.
2. Description of the Related Art
Semiconductor wafer processing comprises a complex series of typically sequential steps through a number of semiconductor processing tools adapted to perform various processes. Such processes include, but are by no means limited to, photoresist deposition, exposure, and development; etching; deposition of conductive and dielectric layers; and planarization. Often, a single wafer may undergo the same operations multiple times as each layer of circuit design is created. Frequently, it is desirable to clean the wafer before certain process steps.
In semiconductor fabricating processes, when one product is manufactured through a plurality of process steps (for example, about a hundred process steps), if a defect occurs in the product it is difficult to figure out which process step caused the failure. Moreover, the financial competitiveness in a manufacturing process depends upon how quickly and accurately the failure can be detected and the cause of the occurrence of the failure can be corrected.
The conventional methods of detecting a process step where a failure has occurred, (i.e., fault correlation) are the commonality analysis method and the physical failure analysis method.
According to the commonality analysis method, the process equipment that performs a process in common to a plurality of failure lots is identified, and thus it is determined that the identified process equipment has caused the failures. However, in order to obtain a statistically significant data set in the conventional commonality analysis method, at least three failure lots need to be generated, and a plurality of failure lots are generally common to not only a failure process step but also a plurality of other process steps. Accordingly, the number of process steps need to be inspected, which increases time and cost.
In the physical failure analysis method, a failure (fault) point of a failure chip is searched, and the failure is directly searched by delayering to the failure point of the failing (faulty) chip. However, in the physical failure analysis method, it is difficult to accurately find out the failure point of the faulty chip, and much time and high cost are required.